1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, a semiconductor memory device equipped with a BIST (built-in self test) circuit.
2. Description of the Related Art
Recently years, as LSIs (large-scale integrated circuit) have been advanced, semiconductor memory devices equipped with mass-storage memories such as DRAM (dynamic random access memory) and SRAM (static random access memory) have been developed. Such semiconductor memory devices are equipped with a BIST circuit.
The BIST circuit has such a structure that the testing function of the semiconductor memory device that is conventionally carried out with a memory tester is incorporated in the form of a circuit on the same chip. The BIST circuit has the functions of inputting test patterns (such as a memory control signal, test address data and data to be written) to devices in a chip, and judge data read from devices in a chip by comparing them with each other whether the data passes or fails.
In the meantime, the electrical fuse (e-fuse) recently began to be utilized for a redundancy of a memory device, as a substitute for the optical fuse (o-fuse), which is conventionally used to rescue memories. The advantages of using the e-fuse are: operations that require blow of fuse with a laser or the like, become unnecessary; memories can still be rescued with use of a tester or the like, not only in the form of wafer but also still after being packaged; and the chip area is expected to be reduced in the future as compared to the case of the o-fuse.
At present, there are some memory devices that use e-fuses only in place of o-fuses. Further, there are many memory devices that use o-fuses and e-fuses in combination to utilize merits of each of these. In memory devices that use o-fuses and e-fuses in combination, the rescue of a defective memory cell detected in the wafer test is assigned to the o-fuses (, which will be called main rescue, hereinafter) and the rescue of a defective cell found in the package test, which is carried out after the assembly, is assigned to the e-fuses (, which will be called secondary rescue, hereinafter).
Here, in the case where there is no memory medium that can store data outside the chip (for example, a memory tester), it is necessary to stop the test each time the address of a defective cell is output during the test by the BIST circuit, rescue the cell using an e-fuse and then re-start the test to continue. Therefore, it is only natural that the time required for the test is longer as compared to the test that judges if a cell passes or fails, and thus the cost for the test is increased accordingly.
Further, the BIST circuit usually carries out many sorts of memory tests. In some cases, data are written in or read from each memory cell a number of times during one memory cell test. Consequently, there is a high possibility that the address of the same defective cell is output in a series of memory tests by the BIST circuit, which makes the test time even longer.
As a technique related to the case of the above-mentioned type, there has been proposed a technique of reducing the memory capacity for storing defective data. (See Jpn. Pat. Appln. KOKAI Publication No. 2002-184197.)